Resistive switching element and use thereof

ABSTRACT

A bipolar resistive switching device (RSM device, FIG.  35 ) comprises an electrically conductive bottom electrode (BE, FIG.  35 ); a stack of transition metal oxides layers (RSM, FIG.  35 ), a number of transition metal oxide layers (RSO, FIG.  35 ) being equal or greater than 2, the stack comprising: at least one MO x  layer (RSOA, FIG.  35 ), at least one oxygen gettering layer NO y  (RSOB, FIG.  35 ). The resistive switching device further comprises an electrically conductive top electrode (TE, FIG.  35 ).

FIELD OF INVENTION

The present invention relates to a resistive switching device consistingof non-stochiometric transition metal oxide stack and more precisely toprocesses for manufacturing such material stack. The present inventionalso relates to a generic memory structure and complementary resistiveprogramming. The present invention further relates to a circuit utilizedfor read/write of memory arrays and the writing protocol methodology.The present invention further encompasses a method of integration ofmemory arrays with the Back End of the Line of the fabricated circuit.

BACKGROUND

Bulk CMOS technologies are predicted to face crucial technologicalchallenges in the next decade. At the same time, novel devices based onResistive Switching Materials (RSM) do not suffer from the sameconstraints and are expected to play a primary role as devices in futureultra-large scale integration technologies, for both memory and logicapplications.

The interest in these devices is motivated not only by their small size,but also their superior characteristics, such as non-volatile memorystorage, two-terminal connection and excellent scalability down to the 1nm range. The RSM, specifically, plays a major role in the currentefforts towards effective implementation of the device for practicalapplications, with manufacturers currently exploring resistive switchingmaterials as future bricks for stand-alone memories as well as forapplications in neuromorphic circuits as well as logic-in-memory.

TaOx/CrOy ReRam Element—Background

In literature, transition-metal oxide memory technologies base theirworking principle on the change of their resistance state due to amodification of the conductivity property of the oxide itself. Two majorgroups of transition metal oxide-based resistive switching elements canbe identified by considering the physical mechanism that drives themodification of the resistance state.

The first group consists of two-terminal devices based on metal/oxideswitches, such as SiO₂, HfO₂ [1] or Al₂O₃ [2]. These devices behave assolid-state electrochemical switches, the resistance of which is definedby a metallic filament formation mechanism related to the solid-stateredox reactions stimulated by the applied electric field [3]. Thewriting mechanism does not require opposite voltage polarities. Thismechanism is also known as unipolar.

A second group is related to the vacancy redistribution in transitionmetal oxide (MO_(x), where M denotes the transition metal, O denotesoxygen and the x is a stochiometric number) layers upon applying avoltage and it causes the switching from an insulating to a metallicstate. For instance, considering TiO₂, the diffusion of oxygen vacanciestransforms the TiO₂ volume into a highly conductive TiO_(2-x) layer,thus reducing the total resistance of the oxide layer. Upon applicationof an electric field with opposite polarity, the redistribution ofoxygen vacancies is led toward the opposite electrode and totalresistance is increased again as the proportion of stochiometric TiO₂increases with respect to TiO_(2-x) Since the writing of this cellrelies on the application of opposite voltage polarities, the writingmechanism is often labeled as bipolar. Note that the unipolar or bipolarnature of the switching functionality in MO_(x) depends also on thechemical nature of the top and bottom electrodes [4].

To summarize the state-of-the-art, note that the resistive memories arecomposed of an oxide mono-layer stacked between 2 metal electrodes.

Generic Memory Structure and Complementary ResistiveProgramming—Background

Future deeply scaled circuits will see their performances limited by thephysical limitations of the materials. To keep pushing the performanceof computation and the density of storage, the microelectronics industryenvisages using more efficient state variable than the electroniccharge. When considering the resistive switching materials, excellentscalability and programming time can be obtained if compared totraditional Flash. This is related to the fact that RSM can be arrangedare simple two-terminal resistive switching devices [1A, 2A].

While a lot of research effort targets high density RSM-based standalonememories [3A], one aim of the present invention is the usage of RSMdevices for Field-Programmable Gate Arrays (FPGAs). The reason behindthis choice is that in reconfigurable logic, up to 40% of the area isdedicated to the storage of configuration signals [4A]. Traditionally,the configuration data is serially loaded in SRAM cells, distributedthroughout the circuit [5A]. As a consequence, circuit power on islimited by slow serial configuration. To overpass SRAM volatility andloading time, Flash NVM have been proposed [6A]. Nevertheless, the useof a hybrid CMOS-Flash technology results in high fabrication cost.Conversely, RSM devices are fabricated within the Back-End-of-the-Line(BEoL) metal lines, moving the configuration memory to the top of thechip and reducing the area utilization[7A]. Similarly, the RSM devicescan be utilized in combination with Through-Silicon-Via (TSVs), enabling3-D stacked FPGA architectures [8A].

With the recent development of RSM technology, a number of novel FPGAbuilding blocks and architectures have been proposed in the past fewyears. For example, routing structures based on RSM devices have shownpromise. In [9A], a cross point for switch-boxes, using the RSM devicesas non-volatile switches, is proposed to route signals throughlow-resistive paths, or to isolate them by means of high-resistivepaths. The concept of routing elements based on RSM switches was thenexploited in [10A, 11A] for timing optimization in FPGAs.

The present invention appear to offer a complete proof of concept of aRSM-based Generic Memory Structure (GMS) circuit for FPGAs fromtechnology development to architectural evaluation. The main idea is toreplace the pass-transistors in SRAM-based FPGAs by RSMs. Hence, theRSMs store the information in their resistive states and can be usedeither to route signals through low-resistive paths, or to isolate themby means of high-resistive paths. Such functionality is used to buildeither routing Multiplexers (MUXs) or configuration nodes. In order tokeep the programming complexity as per SRAM-based FPGAs, we propose anefficient methodology based on the Generic Memory Structure (GMS)complementary programming. The proposed methodology has been validatedby electrical measurements on a fabricated GMS device. Finally, theimpact of the GMS MUXs and configuration memories is studied at thesystem level over a set of complex benchmarks. We show that theGMS-based FPGA reduces area by 7%, while the low on-resistance of RSMdevices provide a gain of 58% in delay compared to SRAM-basedcounterpart.

Read/Write Circuitry—Background

In order to gain full advantages of the RSM device arrays, it is crucialfor the integration to be CMOS compatible, having a thermal budgetcompatible with CMOS Back-End-of-the-Line (BEoL) and the possibility forthe memory array to be integrated into a CMOS chip by post-processing.It is thus crucial that a dedicated read/write circuit is able to tacklethe issues coming from RSM device arrays and specifically implement adedicated read/write protocol.

SUMMARY OF INVENTION

In a first aspect the invention provides a bipolar resistive switchingdevice comprises an electrically conductive bottom electrode; a stack oftransition metal oxides layers, a number of transition metal oxidelayers being equal or greater than 2. The stack comprises at least oneMO_(x) layer, at least one oxygen gettering layer NO_(y). The resistiveswitching device further comprises an electrically conductive topelectrode.

In a preferred embodiment the oxygen gettering layer comprises atransition metal oxide taken from the list comprising: CrO_(y), TiO_(y),HfO_(y), NbO_(y).

In a preferred embodiment a value of the stochiometric number y is inthe range 0<y≦2.

In a preferred embodiment values of the stochiometric number x is in therange 0<x≦2.5.

In a preferred embodiment the metal M is taken from the list comprising:Cr, Ti, Hf, Ta, Nb.

In a preferred embodiment the stack of transition metal oxide layerfurther includes at least one layer of metal (INTE).

In a second aspect the invention provides a process for manufacturing abipolar resistive switching device comprising steps of creating a bottomelectrode from an electrically conductive material, creating a topelectrode from an electrically conductive material, and creating a stackof transition metal oxide layers sandwiched in between the top electrodeand the bottom electrode, a number of transition metal oxide layersbeing equal or greater than 2. The stack comprises at least one MO_(x)layer, and at least one oxygen gettering layer NO_(y).

In a preferred embodiment of the inventive process the oxygen getteringlayer comprises a transition metal oxide NO_(y), wherein the metal N istaken from the list comprising: Cr, Ti, Hf, Nb.

In a preferred embodiment of the inventive process the metal M is takenfrom the list comprising: Cr, Ti, Hf, Ta, Nb.

In a preferred embodiment, the process further comprises a step ofcreating at least one layer of metal to be included in the stack oftransition metal oxide layers.

In a preferred embodiment of the inventive process the step of creatingthe electrically conductive bottom electrode comprises starting from anelectrically insulated Si substrate, and depositing the bottom electrode(BE) lines with a lift-off method, the step of creating the stack ofmetal oxide layers comprises depositing the MO_(x) layer by means ofsputtering from a MO_(z) target, wherein values of the stochiometricnumber z is in the range 0≦z≦2.5, and evaporating a metallic N layerthereby forming the oxygen gettering NO_(y) layer at the interfacebetween N and TaO_(x), and the step of creating the electricallyconductive top electrode comprises starting from the metal oxide layer,and depositing the top electrode lines with a lift-off method.

In a preferred embodiment of the inventive process a value of thestochiometric number y is in the range 0<y≦2.

In preferred embodiment of the inventive process values of thestochiometric number x is in the range 0<x≦2.5.

In a preferred embodiment of the inventive process the electricallyconductive electrodes in the steps of creating the bottom electrode, andcreating the top electrode, and the metal oxide layers in the step ofcreating the metal oxide layers stack, are obtained by deposition stepswhich correspond to one of the following: sputtering deposition;evaporation method; atomic layer deposition.

In a preferred embodiment of the inventive process the step of creatingthe stack of metal oxide layers comprises: depositing the MO_(x) layerby means of sputtering from a MO_(z) target, wherein values of thestochiometric number z is in the range 0≦z≦2.5, and evaporating ametallic N layer thereby forming the oxygen gettering NO_(y) layer atthe interface between N and TaO_(x). The step of creating theelectrically conductive top electrode comprises starting from the metaloxide layer, and depositing the top electrode lines with a lift-offmethod.

In a preferred embodiment of the inventive process the step of creatingthe electrically conductive bottom electrode comprises depositing bottomelectrode lines starting from a CMOS circuit.

In a preferred embodiment of the inventive process the step of creatingthe electrically conductive bottom electrode comprises starting from aCMOS circuit, the CMOS circuit comprising conductive electrode lineswhich are used as the electrically conductive bottom electrode.

In a preferred embodiment of the inventive process the step of creatingthe electrically conductive bottom electrode comprises depositing bottomelectrode lines starting from an electrically insulated Si substrate.

In a preferred embodiment of the inventive process the step of creatingthe electrically conductive bottom electrode comprises starting from anelectrically insulated Si substrate, the electrically insulated Sisubstrate comprising conductive electrode lines which are used as theelectrically conductive bottom electrode.

In a third aspect the invention provides a circuit comprising 2 bipolarresistive switching devices according to the invention, the 2 bipolarresistive switching devices being serially connected in such a way thattheir polarities are opposed.

In a fourth aspect the invention provides a multiplexer circuitcomprising a plurality of bipolar resistive switching devices andtransistors, wherein the bipolar resistive switching devices serve asrouting switching and wherein transistors serve for programming themultiplexer circuit.

In a fifth aspect the invention provides a read/write circuitcomprising: a digital controller that has a digital state machineconfigured to control write operation according to a protocol; and ananalog read circuitry. The latter comprises a high gain differentialamplifier, a current comparator and a current calibration circuitrydesigned for a column, whereby the analog read circuitry comprises ahigh gain operational amplifier (opamp), a voltage comparator and avoltage calibration circuitry. The read/write circuit further comprisesa further analog read circuitry to set each un-selected row voltage tothe same voltage level as the column voltage levels; a reference voltagegeneration block controlled by the digital controller to keep the rowand column voltage levels at sufficient voltage levels in order toprogram a Resistive Switching Material element contents with minimumcurrent consumption; and column and row decoders controlled by thedigital controller to select the appropriate voltage level on theselected row and selected column.

In a preferred embodiment of the read/write circuit a sequence of writeoperations is applied and verified by a sequence of read operations toensure that a specific resistive switching material stores a specificresistance state.

In a preferred embodiment of the inventive programming operation eachone of the voltage signals −5V≦V_(p1)≦+5V, −5V≦V_(p2)≦+5V,−5V≦V_(p3)≦+5V are simultaneously applied to each one of the electrodesforming the circuit, causing the two bipolar resistive switching devicesto simultaneously change resistive state.

BRIEF DESCRIPTION OF THE FIGURES

The invention will now be explained in more detail by describingpreferred embodiments and referring to figures, wherein:

FIG. 1 illustrates an example embodiment of a transition metal oxidebi-layer stack according to the invention;

FIG. 2 illustrates a real device sketch as per the embodiment shown inFIG. 1. (a) 3D cross-point RSM device concept with fence-like TopElectrode (TE) shape. (b) Lateral cross-section view ofPt/TaO_(x)/CrO_(y)/Cr/Cu cross-point RSM device. The fence-like TEenables better scalability of the cross-point device thanks to areduction of the intense electric field distribution at the corners;

FIG. 3 illustrates an example embodiment of a multiple transition metaloxide layer stack according to the invention;

FIG. 4 illustrates an example embodiment of a multiple transition metaloxide and transition metal layers stack according to the invention;

FIG. 5 illustrates a process flow according to an embodiment of theinvention. (a) Insulated Si substrate; (b) Pt bottom electrode lift-off;(c) TaO_(x) sputtering deposition; (d) TE lift-off (e) Sputteringparameters of TaO_(x), with increasing radio-frequency power andconstant 3 sccm/15 sccm Ar/O₂ flows;

FIG. 6 illustrates a Scanned Electron Microscope (SEM) top view of (a)bottom electrode lines; (b) complete 64 bit crossbar array of deviceswith 100 nm half-pitch; (c) reconstructed 3-dimensional (3D) image fromAtomic Force Microscopy (AFM) profile;

FIG. 7 shows a Pt/TaO_(x)/CrO_(y)/Cr/Cu cross-point device with 900nm×900 nm cross-point area. (a) Tilted SEM image view. Notice thefence-like structures at the edges of the TE line. (b) Reconstructed 3DAFM image of the pristine cross-point device. Average roughness on TE isσ≈42.6 nm;

FIG. 8 contains a typical I-V characteristic of thePt/TaO_(x)/CrO_(y)/Cr ReRAM cell showing resistance ratio of 10⁴. Noticevery low V_(SET)=0.8 V and V_(RESET)=−1 V. After fabrication the devicesare forming-free and in the ON state;

FIG. 9 contains a typical I-V characteristic of the Al/TiO₂/Al ReRAMcell after forming with V_(SET)=−1 V and V_(RESET)=+0.8 V. Inset showsV_(FORMING)=−3.4 V;

FIG. 10 contains an X-ray diffraction pattern on a Si waferdemonstrating amorphous TaO_(x)/CrO_(y). The peaks are related to thepresence of Cu and Cr metal layers on top of the TaO_(x)/CrO_(y). The Sipeak comes from the substrate and it has been utilized for thecalibration of the X-ray diffractometer;

FIG. 11 contains a log(I)-log (V) plot of Pt/TaO_(x)/CrO_(y)/Cr/Cu whichshows typical trap-controlled conduction ofSpace-Charge-Limited-Conduction (SCLC) before SET. In the SET region,the slope is about 25 and it is indication of gradual distribution ofdefects;

FIG. 12 contains a log(I)-log (V) plot of the Al/TiO₂/Al which showstypical trap-controlled conduction of SCLC with quadratic V dependencebefore SET condition, thus following Child's law dependence. In the SETregion, the slope is about 50, and it is indication of an abruptdistribution of defects;

FIG. 13 shows an average roughness profiles for TaO_(x) cross-points a)σ≈42.6 nm after fabrication b) σ≈56.3 nm after 100 cycles. Thebroadening is attributed to the structural change induced by the motionof oxygen-vacancies upon cycling;

FIG. 14 contains an XPS depth profile analysis showing the presence ofboth Cr and Ta in oxidized states. Both Ta₂O₅₋

and TaO₂₋

are present, with more conductive TaO₂₋

close to the Pt BE and mixture of TaO₂₋

and CrO_(y) at the Cr/Cu TE;

FIG. 15 shows a cumulative probability of Low Resistance State (LRS),Intermediate Resistance states 1 (IR1) and 2 (IR2) and High ResistanceState (HRS) for Pt/TaO_(x)/CrO_(y)/Cr devices. The LRS, IR1 and IR2 areobtained by using SET pulses of 2 ms, 1 ms and 500 μs at 1 V,respectively. The HRS is obtained with a 500 μs RESET pulse at −1 V;

FIG. 16 shows a cumulative probability of LRS and HRS for Al/TiO₂/Aldevices. The LRS and the HRS are obtained by using SET and RESET pulsesof 500 μs at −1 V and +1 V, respectively;

FIG. 17 shows LRS and HRS resistance distributions for increasingV_(READ) of the Al/TiO₂/Al cell. The 10⁴ resistance ratio is constantover a large range of reading voltage;

FIG. 18 shows measured HRS and LRS values for the Pt/TaO_(x)/CrO_(y)/Crcell devices with different cross-point area demonstrating excellentscalability, indicating local switching at the nanoscale;

FIG. 19 shows resistance distributions for multi-value storages vs.increasing V_(READ) of the Pt/TaO_(x)/CrO_(y)/Cr cell. The HRS, IR2,IR1, LRS are encoded in 2 bit;

FIG. 20 shows a baseline FPGA architecture [5A] (top) and FPGAsarea/delay/power repartition per resources [4A] (bottom);

FIG. 21 contains (a) Si wafer coated with 100 nm ALD Al₂O₃ insulationlayer. (b) Horizontal Al metal lines deposited with lift-off defined bye-beam lithography. (c) 10 nm thick TiO₂ layer deposited with ALD. (d)Vertical Al metal lines deposited as per (b) forming the top electrodes.(e) A 64-bit crossbar prototype array with 200 nm half-pitch. (f) RSMshowing bipolar resistive switching (500 nm half-pitch cell). After theforming process SET and RESET occurs at negative and positive topelectrode voltages;

FIG. 22 contains (a) a Cross sectional schematic showing the integrationof a RSM device integrated between the M1 and M2 interconnection levelsin the back-end-of-line. The bottom electrode is thus directly connectedto a MOSFET selector (bottom) forming a 1-Transistor 1-Resistor (1T1R)memory node; (b) RSM device polarity selection by physical design;

FIG. 23 schematically illustrates GMS complementary programming;

FIG. 24 contains a graph showing complementary switching operation forthe RSM-based GMS;

FIG. 25 illustrates 4 to 1 multiplexers based on (a) pass-gates and (b)ReRAMs;

FIG. 26 illustrates (a) 4 to 1 multiplexer with programming circuits and(b) associated programming diagram to configure output to input D1;

FIG. 27 shows (a) RSM-based memory node; (b) Node in read configuration;and (c) Node in write configuration;

FIG. 28 contains a line sharing illustration in standalone-memory-likearchitecture;

FIG. 29 contains a graph showing an electrical simulation of a GMS-based2 to 1 MUX timing response;

FIG. 30 contains a bar graph illustrating delay estimation for FPGAssynthesized with ReRAM- and SRAM-based multiplexers;

FIG. 31 illustrates one of the read operation method over 2^(n)×2^(m)RSM stack array cells (1), according to a preferred embodiment of theinvention;

FIG. 32 illustrates another method of the read operation over2^(n)×2^(m) RSM stack array (1), according to a preferred embodiment ofthe invention;

FIG. 33 shows the write operation over 2^(n)×2^(m) RSM stack array (1),according to a preferred embodiment of the invention;

FIG. 34 illustrates the writing protocol in order to control VPGM andVLH voltage levels, according to a preferred embodiment of theinvention;

FIG. 35 shows the elements of an RSM stack, according to a preferredembodiment of the invention;

FIG. 36 shows a CMOS with an MMC layer that is connected through a VIAto the top metal electrode, according to a preferred embodiment of theinvention;

FIG. 37 shows a CMOS that involves additional one or two lithographicsteps in order to obtain a RSM stack in between the last metal layer andthe last via layer, according to a preferred embodiment of theinvention;

FIG. 38 shows a CMOS die fabricated such that the last CMOS BEoLincludes patterns that can be used as a mask for the definition of topelectrodes, according to a preferred embodiment of the invention; and

FIG. 39 shows a detail of a post-processed CMOS die, for which thepassivation of the top two metal layers has been etched, according to apreferred embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION General Description of the ReRamSwitching Device

The present invention provides a device consisting of one—ormore—stacked layers of non-stochiometric transition metal oxides MO_(x)and a non-stochiometric oxygen gettering layer also made of transitionmetal oxide NO_(y) sandwiched between two metal electrodes. Theapplication of an electric field between the two metal layers imposes acurrent flux through the transition metal oxide stack (RSM stack), whichmight cause an individual resistive switching of the transition metaloxides composing the stack upon application of a sufficiently large(positive or negative) electric field.

This structure differs from the typical RSM stack where only one oxidelayer type is utilized to form a RSM device.

The present invention further provides a method for obtaining the deviceas described herein.

First Embodiment

In a first embodiment, the device consists of a bi-layer oxide stack(TaO_(x)/CrO_(y)) sandwiched between 2 metal electrodes. The associatedfabrication process flow can be sketched as the following:

after the bottom electrode is fabricated (FIG. 1-a), a 1^(st) oxidelayer is created (FIG. 1-b). The oxide can be formed by oxidation of thebottom electrode, or by deposition of the oxide with sputtering orevaporation or atomic layer deposition methods. A 1^(st) oxide layer isformed on top or around the bottom electrode. Then a 2^(nd) oxide layeris formed on top of the 1^(st) oxide layer (FIG. 1-c). After the 2^(nd)oxide layer is formed, a top electrode is deposited on top of the 2^(nd)oxide layer (FIG. 1-d).

Note that the deposited materials might results of:

-   -   the forming of an oxide stack with stochiometry, with x ranging        from 0<x≦2.5 and y ranging from 0<y≦2;    -   the combination of graded TaO_(x) and/or CrO_(y) and        stochiometrically-defined TaO_(x) and/or        stochiometrically-defined CrO_(y);    -   the forming of TaO_(x) and/or CrO_(y) layers are doped with any        of the elements of the periodic table.

More precisely, the device scheme is shown in FIG. 2-a. The deviceconsists of a Bottom Electrode (BE), a stack of TaO_(x) and CrO_(y)oxides and Cr/Cu Top Electrode (TE), as depicted in FIG. 2-b. Note thatthe layers shape (fence like) enables better scalability thanks to areduction of the intense electric field distribution at the corners.

Generally, the process includes creating a bottom electrode, which ismade of an electrically conductive or semi-conductive material, anelectrically conductive TE and an oxide stack sandwiched in between TEand BE. The fabrication starts from an electrically insulated Sisubstrate or from a fabricated CMOS circuit, then BE lines are depositedwith a lift-off method. Then a 1^(st) oxide is deposited by means ofsputtering of TaO_(x) from a Ta₂O₅ target. Then a metallic Cr layer isevaporated and a 2^(nd) oxide CrO_(y) forms at the interface between Crand TaO_(x). Finally a Cu top electrode is evaporated. Cr and Cu arepatterned with a lift-off technique. Application of the proposed flow toa real test stack is given in the next section.

Device Fabrication

The device concept is a cross-point of 2 metal lines with a transitionmetal oxide sandwich (FIG. 2-a). The shape of the TE is optimized toimprove scalability (FIG. 2-b). Bulk-Si wafers are isolated bydepositing 100 nm thick Al₂O₃ with Atomic Layer Deposition (ALD) (FIG.5-a). Then, PMMA bi-layers are patterned with e-beam lithography aslift-off masks for 10 nm/80 nm Pt BE deposition (FIG. 5-b). In the nextstep, a second lift-off mask is defined and 15 nm TaO_(x) oxide layer(FIG. 5-c) is deposited by sputtering from a Ta₂O₅ target withincreasing radio frequency power in Ar/O₂ atmosphere (FIG. 5-e).Finally, 50 nm/100 nm thick Cr/Cu bi-layers TE are deposited by e-beamevaporation (FIG. 5-d). For Al/TiO₂/Al devices, the Al electrodes aredeposited with e-beam evaporation while 10 nm thick TiO₂ is deposited byALD. In FIG. 6-ab SEM images of 100 nm wide BE lines and 64 bit passivecrossbar (consisting of BE lines, transition metal oxide stack and TElines, being the BE lines and the TE lines arranged orthogonally) areshown, respectively. In FIG. 6-c, a 3D reconstructed AFM profile isshown. About 250 individual Pt/TaO_(x)/CrO_(y)/Cr cross-points for areasizes varying from 100 nm×100 nm to 1 μm×1 μm, and 64 bit cross-barswith half-pitch varying from 100 nm×100 nm to 500 nm×500 nm are built onthe same sample following the proposed fabrication steps. In FIG. 7-ab,a tilted SEM view, and a 3D reconstructed AFM profile of a cross-pointdevice with fence-like TE are shown.

Device Characterization

Electrical measurements are carried out with an Agilent B1500semiconductor device analyzer. Pulse mode sweeps with pulses of 500 μsdemonstrate forming-free Bipolar Resistive Switching (BRS) forPt/TaO_(x)/CrO_(y)/Cr (FIG. 8). The BRS is obtained for a voltage rangeof less than 1 V with pristine ON state in the same range of the LowResistance State (LRS). This is an important advantage compared with nonforming-free RSM devices, because the forming operation requires highervoltages. A forming voltage of −3.4 V has indeed been necessary for theAl/TiO₂/Al (FIG. 9), that then show similar performance as thePt/TaO_(x)/CrO_(y)/Cr devices.

Switching Mechanism

Material characterization has been carried out to understand thepristine ON state of Pt/TaO_(x)/CrO_(y)/Cr. The X-ray diffractionpattern of FIG. 10 shows peaks from the TE and the Si substrate. Theabsence of any Ta₂O₅ or TaO₂ peaks indicates that the material is inamorphous state, due to the low deposition temperature. The pristine ONstate excludes the conductive filament mechanism and observing thedouble logarithmic plot of the I-V curve (FIG. 11), quasi-Ohmic regimeswith slopes ≈1 are obtained for regions far from the SET condition.Typical trap-assisted Space-Charge-Limited-Conduction (SCLC) is observedclose to the SET condition. The SCLC conduction is also observed forAl/TiO₂/Al devices (FIG. 12) whose slopes indicate a more abruptdistribution of trap density, which can be related to the differentdeposition methods. In both devices, the resistive switching mechanismcan be attributed to Redox reaction linked with the motion ofoxygen-vacancies [5,6]. Moreover, structural modification is observedfrom the roughness profile of Pt/TaO_(x)/CrO_(y)/Cr cross-point after100 cycles. As shown in FIG. 13, the Pt/TaO_(x)/CrO_(y)/Cr averageroughness (Ra) measured above the TE broadens upon cycling. The Rachanges from a pristine 100 nm variation (FIG. 13-a) into a 200 nm broadwindow (FIG. 13-b), indicating structural modification by the motion ofoxygen vacancies upon switching. In addition, XPS-depth analysis (FIG.14) confirms that Ta₂O₅₋

and TaO₂₋

are present, with more conductive TaO₂₋

close to the Pt BE and mixture of TaO₂₋

and CrO_(y) at the Cr/Cu TE which is consistent with a Redox switchingmechanism.

Multi-Values Programming

Several resistance levels of Pt/TaO_(x)/CrO_(y)/Cr devices can beprogrammed. As shown in FIG. 15, four levels of resistance (encoding 2bit) are found within a 4 orders of magnitude range. A larger resistancewindow of 1 bit is found for Al/TiO₂/Al devices, which show a LRS around30Ω and a High Resistance State (HRS) at 1 MΩ within 2 orders ofmagnitude variation (see FIG. 16). The Al/TiO₂/Al show stable LRS andHRS in a large V_(READ) voltage range (FIG. 17). ThePt/TaO_(x)/CrO_(y)/Cr devices demonstrate excellent scalability, as theHRS/LRS ratio improves for smaller device sizes (FIG. 18). For instance,2 bit can be written in a Pt/TaO_(x)/CrO_(y)/Cr by using shorter SETpulses in order to program the cell in one of the stable IntermediateResistance (IR) states. An example of 2 bit storage using LRS, HRS and 2IRs is demonstrated in FIG. 19, each level is separated of about oneorder of magnitude from each other for various V_(READ). The devicescould be easily assembled into dense 2.5×10⁹ bit/cm² passive crossbararrays whose storage density improves to 10¹⁰ bit/cm² thanks to thecapability to store multiple resistive levels of Pt/TaO_(x)/CrO_(y)/CrRSM devices.

Second Embodiment

As a second embodiment, the device consists of a stack including TaO_(x)and/or CrO_(y) layers that are inter-mixed or inter-spaced withadditional oxide layers made of transitional metal oxides. In thisembodiment, a BE is deposited on a substrate (FIG. 3-a). Then, a 1^(st)oxide layer is formed on top or around the bottom electrode (FIG. 3-b).Then several layers of oxides are formed sequentially on top of theprevious oxide layers (FIG. 3-c). Finally a TE is deposited on top ofthe last oxide of the stack (FIG. 3-d).

Third Embodiment

As a third embodiment, the device consists of a stack formed by severallayers of transitional metal oxides and metals. In this embodiment, anelectrically conductive BE is formed (FIG. 4-a). Then, a 1^(st)transition metal oxide layer is formed on top or around the BE (FIG.4-b). After the 1^(st) oxide layer is formed, another transition metalis deposited and an interface with mixture of elements of the 1^(st)oxide and the deposited transition metal is also formed (FIG. 4-c). Thenanother sequence of transition metal oxides and transition metals isformed, such that interfaces of transition metal oxide layers andtransition metal layers are formed (FIG. 4-d). Finally a TE is depositedon top of the stack (FIG. 4-d).

Invention Impact Perspective Performance

-   -   Low voltage operation (1V range): this enables the use of the        RSM device into scaled technologies, for which the CMOS circuit        cannot operate with voltages larger than 1V.    -   Multi-value resistive states: this feature improves the number        of data stored per RSM device, thus increasing the density of        the stored data;    -   Pristine ON condition: this feature enable to have RSM devices        in the low resistive state already after fabrication, thus there        is no need of a forming free step with special forming voltages        to enable a correct functionality of the RSM device itself.    -   Forming Free: as per the pristine ON condition, this feature        allows to avoid forming operations before the RSM device can be        used for the normal operations of writing, reading, etc. . . .    -   Bipolar Resistive Switching: this feature enables the use of        voltages with opposite polarities for SET and RESET operations;    -   R_(on)/R_(off) ratio up to 6 orders of magnitude: the large        resistive ratio enables to improve the noise margin for the        circuits that are implemented for writing and reading the RSM        devices.    -   Scalability down to 1 nm cross-point: this feature is important        to increase density for very advanced technology nodes and it        gives perspective for its use in the next decades.

Prospective Applications

-   -   FPGAs (forming free, bipolar resistive switching, low voltage,        R_(on)/R_(off) ratio): In FPGAs, RSM devices can be used as        routing resource by employing the resistance into an RSM as a        switch. Moreover, two or more bipolar resistive switching RSM        devices can be connected in such a way that a complementary        resistive switching cell (e.g. GMS) is formed. This is        beneficial for efficient programming of the RSM-based routing        resources. Similarly, RSM-devices can also be used as standalone        memories in FPGAs. The low voltage operation and the high        Resistance Ratio enable to scale the technology and to improve        noise margins, respectively.    -   Standalone memories (R_(on)/R_(off) ratio, Multi-value,        Scalability): a large Resistive ratio enables to improve noise        margin, thus relaxing the requirements for the peripheral        circuitry needed for the read/write operations in standalone        memories. It is important to notice that the scalability and the        multi-valued features are extremely important for standalone        memories to be competitive.    -   Dense cross-bars (scalability, multi-value, . . . ); As per the        previous application, the scalability and the multi-value        features are keys for dense cross-bar applications.    -   Neural Networks (multi-value, scalability): The RSM-devices can        be implemented in neuromorphic circuits in specific blocks. For        instance, the RSM can be utilized to emulate the artificial        synapse behavior. Due to the requirements of a large number of        synaptic interconnections and the capability to store a range of        resistance states to express potentiation and/or depression of a        synaptic interconnect, multi-value and scalability features are        also very important.

General Description of the Memory Structure and Complementary ResistiveProgramming

The development of the memristor enables new possibilities forcomputation and non-volatile memory storage. The present inventionrelates to a resistive switching element consisting of two resistive RAMin series connected and to a way of programming the resistance state ineach of the two RSMs. We propose a Generic Memory Structure (GMS) anddepict its interest for 3D FPGA applications. The GMS cell isdemonstrated to be utilized for steering logic useful for multiplexingsignals, thus replacing the traditional pass-gates in FPGAs. Moreover,the same GMS cell can be utilized for programmable memories as areplacement for the SRAMs employed in the look-up tables of FPGAs. Afabricated GMS cell is presented and its use in FPGA architecture isdemonstrated by the area and delay improvement for several architecturalbenchmarks.

Architectural Background and Motivation

FPGAs are regular circuits formed by several identical reconfigurablelogic blocks called Configurable Logic Blocks (CLBs) that are surroundedby reconfigurable interconnect lines [5A]. As depicted in FIG. 20, everyCLB is formed by a set of N Basic Logic Elements (BLEs). A BLE is simplya K-input Look-Up-Table (LUT), whose output can be routed to any otherLUT input with or without being saved in a flip-flop. Every CLB has Iinputs coming from other CLB outputs. All design parameters N, K and Ican be set by the FPGA architect depending on the targeted systemgranularity.

Programmable interconnections between the different blocks are realizedby a massive number of multiplexers configured by memory cells. FIG. 20depicts also the area/delay/power breakdown of the various components ofa baseline SRAM-based island-style FPGA. It is noteworthy that thecustomizable resources play a major role in FPGA performance,contributing to more than 80% of the total area and delay. For thisreason, the FPGA architecture can be improved by working on memories andtheir efficient use in routing operations.

ReRAM Technology

Many different RSM technologies are currently investigated. In thissection, we will draw some generalities and present the fabricationflow.

General Considerations

Oxide memory technologies base their working principle on the change inresistance state due to a modification of the conductivity. Differentphysical mechanisms can be identified in the switching of RSMs [1A]. Inthe following, we will focus only on the Bipolar Resistive Switching(BRS) mechanism [2A]. The BRS mechanism is related to the oxygenvacancies redistribution in TiO₂ layers upon application of a voltageacross the transition metal oxide, causing a resistance change from lowto high and vice-versa depending on the voltage polarity. In thefollowing, the electrode on top of the RSM structure is defined as thepositive electrode.

Experimental Process Flow

The fabrication flow of the test structures started from bulk-Si waferspassivated by a 100 nm thick Al₂O₃ layer deposited by Atomic LayerDeposition (ALD) (FIG. 21-a). Next horizontal 70 nm thick BottomElectrode (BE) lines were patterned by lift-off and e-beam evaporation(FIG. 21-b). Then, for some devices a 10 nm thick TiO₂ layer wasdeposited with ALD (FIG. 21-c). For other devices a 50 nm thick TiO₂ wasdeposited by reactive sputtering of a Ti target in O₂/N₂/Ar atmosphereat room temperature. Finally, vertical Top Electrode (TE) lines of thecrossbar were defined with a second lift-off together with contact areasfor electrical characterization (FIG. 21-d). The fabrication method wasdemonstrated for crossbar arrays with half-pitch down to 100 nm. In FIG.21-e, a 64-bits crossbar memory cell with 200 nm half-pitch is shown. InTable I several electrode combinations of TE and BE materials arereported.

Experimental Measurements

To achieve consistent BRS, a forming step with low current compliance(<100 μA) was performed. A typical forming voltage above+3.5V was foundfor a positive TE voltage, while the BE was grounded. Then consistentBRS achieving R_(ON) and R_(OFF) resistive states was measured (FIG.21-f). Forming operation is not suited for highly distributed memoryapplications, such as FPGAs. Nevertheless, forming-free RSM-devices canbe fabricated by the use of different methods, and in this study the twodevices with TiO₂ deposited by reactive sputtering switch without theneed of a forming step (Table I). This can be attributed to the moredefective structure of sputtered TiO₂, which typically consists of anheterogeneous mixture of different transition metal oxide phases.

Storage Element Integration Flow

One of the big advantages of RSM technology is its CMOS-compatibility.The materials involved in RSMs are deposited at low temperature and canbe integrated into the Back-End-of-The-Line (BEoL). As an illustration,a schematic cross section of a co-integrated RSM device in series with aCMOS transistor is shown in FIG. 22-a. As in standalone NOR arrays,illustration includes a storage node and a selector transistor in seriesin the 1-Transistor 1-Resistor (1T1R) configuration. The memory elementmay be fabricated either just after the Si contact formation step orafter the first steps of interconnections (e.g. on top of Metal 1interconnect level).

Generic Memory Structure

In order to simplify the programming scheme, a GMS structure consistingof two RSM devices connected in series is introduced.

GMS Concept

As per the previous section, RSMs can be fabricated within the BEoLprocessing. Hence, it is possible to fabricate them between two metallayers (e.g. in between Metal 1 and Metal 2, as depicted in FIG. 22).Because of the BRS of the RSM devices of this study, depending on theforming polarity, either the Metal 1 or the Metal 2 terminal can beutilized as the positive electrode of the memory, giving two possibleconfigurations (see FIG. 22-b).

In the GMS, two RSM devices are interconnected as shown in FIG. 23-a.The positive terminal of the top device is connected to the negativeterminal of the bottom device. This arrangement enables complementaryprogramming of the two RSM devices composing a GMS. We call theconcurrent programming of the GMS a complementary programming operation.A similar programming scheme was previously used for low power crossbars[12A]. FIG. 23-b illustrates the programming of the top path (i.e. leftto right arrow in the programming graph shown in FIG. 23-d). R₁ and R₂are switched simultaneously to R_(OFF) and to R_(ON) respectively. Thisoperation is achieved by grounding the common right terminal and biasingthe left terminal to V_(th) (which corresponds to the SET voltage−V_(th) for R₁ and to the RESET voltage +V_(th) for R₂). Programming thebottom path (see FIG. 23-c) is done by inverting V_(th) and Gnd (whichcorresponds to the RESET voltage for R₁ and to the SET voltage for R₂).In addition to increasing the programming speed, only two voltages areneeded (Gnd and V_(th)), thanks to the complementary scheme.

Experimental Validation

The complementary programming operation has been validated by electricalmeasurements, while the MUX performances have been extracted byelectrical simulations.

FIG. 24 depicts the resistance values of R₁ and R₂ of an GMS-basedMUX21. Resistances are read at V_(READ)=+0.1V.

After a preliminary forming step, R₁ and R₂ are set to R_(ON). Thedevices are then read for 10 cycles, showing a stable non-volatileresistance. Hence R₁ and R₂ are switched using the complementaryprogramming operation presented in the previous section. During thefirst write operation SET and RESET events are induced on R₂ and R₁,respectively (see FIG. 23-c) by applying a voltage pulse for 500 μs.After reading the resistance values for another 10 cycles, againvalidating the non-volatility of the resistance states, a secondcomplementary switching operation is performed as depicted in FIG. 23-b.Now the resistance states of R₁ and R₂ switch complementary, as seen inthe reading sequence of FIG. 24. Note that the resistance values of R₁and R₂ do not exactly match. This is due to the different RSM devicegeometries and to the large variability of the cells utilized for thedemonstrator. Nevertheless, improved variability of one order ofmagnitude has been demonstrated for RSM device prototypes fabricatedwith industrial methods [2A].

GMS-Based FPGA Design

In this section, the operation of a novel multiplexer design and aconfiguration memory based on GMS is discussed.

GMS-Based Multiplexer: Overall Structure

FIG. 25-a illustrates a 4 to 1 MUX based on CMOS transmission-gatesarranged in two cascaded stages. In this MUX, a unique path isconfigured between an input D_(X) and the output Y. The path is selectedby the signals S_(X). Adjacent paths are complementary addressed byinverted signals SN_(X). The selection signals are permanently driven toensure a constant path selection. Inspired by this structure, theRSM-based MUX (depicted in FIG. 25-b) uses the unique low on-resistanceproperty of the RSM-devices to operate as high-performance non-volatileswitches. Thus, it is possible to replace the transistor-basedpass-gates by the RSM-devices to obtain a non-volatile MUX. The pathselection operation is achieved by programming to low resistance stateall the individual memories that belong to the desired path. The otherspaths are deselected by programming their memories to high resistancestate.

GMS-Based Multiplexer: Configuring the MUX Network

For each RSM-device composing the MUX structure, a high- or alow-resistive state must be programmed. This individual selection andwrite operation leads to an increase in the programming complexity. Inorder to simplify this, a complementary programming scheme for theRSM-device network is proposed here. Complementary programming isexplained for a 4 to 1 MUX, however it can be generalized to a genericMUX. A two stage 4 to 1 MUX and its programming circuit are shown inFIG. 26-a. By enabling the V_(P) signal (V_(P)=1), all the input andoutput nodes of stage i are shorted to the output of the configurationflip-flops Q_(i) and Q_(i+1) respectively. In the example of the FIG.26, nodes n1 to n4, n5 and n6, and n7 are connected to Q₁, Q₂, and Q₃respectively. In order to avoid cross programming between differentstages, each stage is configured sequentially. Hence, for a two stageMUX network, we need two steps for configuring a unique path. As anexample, we illustrate the two steps required to configure the pathconnecting input D₁ to the output Y. All the configuration transistorsare first turned Off (V_(P)=0). A set of digital logic levels is thenserially fed to the shift register. Voltages are chosen to configure thestage in the desired state without interfering with the other stages.FIG. 26-b presents the configuration scheme for programming the twostages sequentially. In the first step (Step 1), the first stage isconfigured to enable the RSM-device connected to the input D₁. This isachieved by applying Q₁=Gnd and Q₂=V_(th). Programming of the successivestages is disabled by applying the same voltage at Q₂, to the upstreamstages (i.e., Q₃=V_(th)). It has to be noted that with this operationalso the RSM-device connected to the input D₃ is enabled. After storingthe desired voltages in the registers, the configuration transistors areturned On (V_(P)=1) and the basic elements of the stage are programmedin the desired state. After the RSM-device programming, all theconfiguration transistors are turned Off. In the next step, theprocedure is repeated for the second stage, which is configured byenabling the RSM-device path between nodes n5 and n7. This is achievedby applying Q₂=V_(th) and Q₃=Gnd. At this point, the first stage is keptstatic, without any programming, by applying the same voltage as Q₂, tothe downstream stages (i.e., Q₁=V_(th)).

GMS-Based Configuration Memory

In this section, we present an elementary circuit used to move most ofthe configuration part of reprogrammable circuits to the fabricationback-end, reducing their impact on fabrication front-end occupancy. Sucha memory node is dedicated to drive LUT inputs. The memory node is basedon a unique GMS node and provides intrinsically the retained informationas a voltage level. Furthermore, it allows an efficient layout bysharing lines.

GMS-Based Configuration Memory: Overall Structure

The basic memory node is presented in FIG. 27-a. The circuit consists of2 RSM-devices connected in a voltage divider configuration between 2fixed voltage lines (L_(A) and L_(B)). The memories are operated in acomplementary manner, in order to improve reliability. The output isdesigned to place a fixed voltage on a conventional standard cell input.Read operations are intrinsic with the structure, while programming isan external operation to perform on the cell.

GMS-Based Configuration Memory: Read Operation

A voltage divider is implemented in this topology to intrinsicallyrealize the conversion from a bit of data stored as resistance level toa voltage level. FIG. 27-b presents a configuration example where thenode stores a ‘1’. Voltage lines L_(A) and L_(B) are respectivelyconnected to V_(ss) and V_(dd). For the sake of illustration, considerthat the resistive memory R₁, connected to the V_(dd) line, isconfigured to the low resistivity state. The other memory R₂, connectedto V_(ss), is in the high resistivity state. As a consequence, a voltagedivider is configured and the output node is charged close to thevoltage of the branch with a high conductivity. The logic levels dependon R_(ON) and R_(OFF) as per the voltage divider structure.

It is also worth noticing that in continuous read operation, a currentwill be established through the resistors. This leads to a passivecurrent consumption through the structure, which is highly dependent onR_(OFF). This static current can be reduced by the choice of a memorytechnology like Cu/TiO₂/Pt (Table I) maximizing the R_(OFF) value,without any impact on the speed. Indeed, the configuration memories arenot directly related to the data path and only drive static nodes.

GMS-Based Configuration Memory: Write Operation

FIG. 27-c presents the programming phase of the node. First, the linesL_(A) and L_(B) are disconnected from the power lines and connected tothe programming signals. The programming signals are chosen according tothe GMS programming scheme. FIG. 28 presents the programming circuitsrequired to program an array of GMS-based configuration memories. Toprovide individual access, each GMS has its own selection transistor.Thus, the different lines can be shared in a standalone-memory-typearchitecture, yielding a more efficient layout. The different modes andprogramming signals are selected by line-driving MUXs.

Performance Characterization

In this section, evaluation of the GMS-based FPGA elementary blocks isproposed at the circuit level. The study focuses on the block-levelmetrics such as area, programming time and energy.

Methodology

To validate the RSM-based building blocks, we characterized theirperformances metrics in terms of area and write time. The performanceextraction is based on the node complexity expressed in terms of thebasic elements that are required to realize the circuit. The area isextracted from basic layout considerations using CMOS 45-nm technologyrules [13A] and expressed in half-pitch to give values independent oflithography node. Timing and energy numbers are extracted from the ITRS[14A]. Comparison with building blocks traditionally used in FPGA, suchas CMOS SRAM 5T cells [5A] and Flash memory elements [6A], are then usedto evaluate the structures. The associated numbers are also extrapolatedfrom the ITRS [14A]. Note that we are dealing with non-volatilememories. Hence, we will stress the comparison with regards to Flash.

Memory Performance Characterization

Table II shows some characterization results in terms of area, writetime and programming energy for the proposed solution and traditionalFPGA memory nodes. Note that this comparison only considers the storagenode itself and is not including all the external programming circuitry.We observe that the proposed RSM-device is the most compact solutionwith a gain of 3× compared to Flash, even with the impact of theprogramming current on the access transistor. This advantage is due tothe reduction of the memory front-end footprint to only one transistor,compared to 5 for the SRAM cell and 2 for the Flash solution (onepull-up transistor coupled to a floating gate transistor). In addition,RSM-devices offer a significant writing time and programming energyreduction for non-volatile memory technologies of 16× and 8×respectively. Finally, note that the leakage power depends mainly on thematerial. Materials with a high R_(OFF) should be privileged for lowpower operation. Indeed, Cu/TiO₂/Pt demonstrates a gain of 2 orders ofmagnitude compared to SRAMs.

Data Path Impact Characterization

FIG. 29 depicts the timing response of the 2 to 1 basic multiplexer. Theelementary multiplexer structure is build with a unique Pt/TiO₂/Pt-basedGMS. The timing response was obtained by electrical simulation andcompared to a CMOS equivalent counterpart built in 45 nm technology[13A]. We observe a timing improvement of 4.5 times as compared to CMOS.This remarkable delay reduction is due to the low on-resistance of theReRAM technologies. For instance, at 45 nm the internal resistance of ann-type transistor is 3.8 kΩ (minimal size transistor extracted from 45nm design kit [13A]), while the RSM technology exhibits an on-resistanceof hundreds of Ohms. Note that, in the proposed MUX design, theprogramming circuits are not related to the data path. Thus, only theRSM parameters impact the electrical performance. Finally, as thememories are directly used to perform the routing operation, no leakagepower is dissipated by the MUX (i.e. no permanent leakage path exist inthe structure), offering significant interest for power reduction.

Architectural Impact

The demonstrated structure introduces compact RSM-devices with lowon-resistance in the data paths of the FPGAs. In this section, we willstudy the impact of the structure on an architectural perspective.

Methodology

A set of logic circuits taken from the MCNC benchmark were used, whichhave been synthesized using ABC [15A]. The technology mapping was thenperformed with a library of 4-input LUTs (K=4) using ABC as well.Subsequently, the logic packing of the mapped circuit into CLBs was donewith N=10 BLEs per CLB and I=22 external inputs using AA-PACK [16A].Finally, the placement and routing were carried out using VPR6.0 [16A].Each benchmark was first synthesized on an SRAM-based FPGA in the CMOS45 nm process [13A]. Then, the SRAM-based MUXs were replaced by theirRSM-device counterparts (Pt/TiO₂/Pt). The impact of the circuits neededfor the programming is taken into account for the evaluations.

Simulation Results

The benchmarks were mapped in CMOS SRAM-based and RSM-based FPGAs. Thecritical path delay estimation is shown in FIG. 30. The benchmarksshowed an area reduction ranging from 4% to 8%, with 7% on average,coming from a slight reduction of the silicon surface occupied by therouting resources. Note that the complete set of programming resourceshave been considered. The simulations showed a critical path delayreduction ranging from 43% to 73%, with 58% on average. The reduction isthe direct impact of the high performances MUXs, introduced throughoutthe data path. This makes the RSM-based FPGA potentially faster than theSRAM-based counterparts. In addition, the leakage power of the CLBs isreduced by 10%, thanks to in-existence of leakage current in the MUXstructure.

Discussions

The bipolar resistive switching RSM-devices presented in thisdescription have been fabricated and electrically characterized in termsof R_(ON)/R_(OFF) ratio and read/write voltages for a differentcombination of metal electrodes with sputtered or ALD deposition ofTiO₂. As reported in Table I, the cells with sputtered TiO₂ are the onlyones showing resistive switching without the need of a forming step.RSM-devices made of Pt/sputtered TiO₂/Pt has been chosen to carry outthe architectural simulations for FPGA because of a betterR_(ON)/R_(OFF) ratio and the compatibility with a ±2 V programmingvoltages. The GMS cells are utilized to replace SRAM LUTs in FPGAs in amore compact way because RSM-devices are implemented into the BEoL.Moreover, the complementary switching mechanism of the GMS cells isutilized also as steering logic. In particular, the low R_(ON) memoriesimprove the delay in the data paths of FPGAs. Last but not least,RSM-devices can be built in different flavors, depending on theobjectives in terms of delay and power trade-off. For instance, theCu/sputtered TiO₂/Pt RSM-device of Table I can be exploited for itslarge R_(OFF). Such a material leads to a reduction of the CLB staticpower consumption of up to 69% compared to SRAM FPGAs.

Prospective Applications

-   -   Reconfigurable Logic (FPGA/CPLD/PLA/NoCs, . . . ): logic gates        can be routed and the routing can be programmed by a network of        GMS cells to program a circuit to provide a specific logic        function;    -   stand-Alone Memories: use of the GMS structure as a unique        memory node to reduce the leakage and simplify the read/write        thanks to unbalanced flip-flops.

General Description of the Read/Write Circuitry

The present invention encompasses, among other objects, a read/writeCMOS circuitry optimized for the read/write operations of RSM arraysimplementing a dedicated read/write protocol.

The present invention gives the method/s of novel read/write circuitryof the resistive memory array cells that requires no pass transistorprocessed underneath each of the memory array cell to select the memorycell in order to perform read or write operation on the selected cell.In order to exploit the functionality of the RSM, the RSM is connectedbetween two conductive electrodes, usually referred as the Top Electrode(TE) and the Bottom Electrode (BE), forming an RSM device. Moreover, inVery-Large-Scale of Integration (VLSI) circuit design, it is highlydesirable to have RSM devices implemented in very dense arrays, thusforming dense arrays of RSM devices arrays.

The present invention further provides a method of integration of RSMdevices arrays on top of CMOS circuitry by post-processing the same CMOSdie where the read/write circuit has been first fabricated. In oneembodiment, the method includes the design of the RSM device to beutilized in the RSM device array integration. In another embodiment, themethod includes the design of the BEoL such that it does not requireadditional masks to pattern VIA, electrodes and resistive switchingmaterials but only micro-fabrication post-processing steps. In anotherembodiment, the method of integration utilizes one or more masks todefine the area of the BEoL where the RSM device arrays are designed tobe performed. In another embodiment, the method of integration utilizesboth the features designed in the BEoL and additional masks to fabricateRSM device arrays.

The invention herein described thus provides a unique combination,specifically with respect to the following points:

-   1. Digital circuit design for the implementation of a dedicated    read/write protocol for RSM memory arrays;-   2. Analog circuit design; and-   3. CMOS BEoL compatible post-processing of the CMOS chip and arrays    of RSM devices integrated by such post-processing.

Preferred Embodiments

The development of a process flow compatible with CMOS Back-End-of-Lineis fundamental for providing large access to this novel technology witha limited development costs. The main objective is to develop someintegration techniques that allow to efficiently implement arrays of RSMdevices on top of dies, processed by conventional CMOS foundries.

One of the big advantages of the RSM technology is itsCMOS-compatibility. Indeed, the materials involved in RSM devices can bedeposited at low temperatures, compatible with metal linemicrofabrication processes (e.g. BEoL). Different integration optionsmight then be envisaged according to a specific RSM device.

First Example Read Circuitry—Method I

The read circuitry shown in (2) in FIG. 31 needs to be implemented foreach of the column cells. Each column voltage level is set by the VREFvoltage through the differential amplifier with high gain. And each rowvoltage level except the row to be read is set to VREF through thecircuitry marked as (3) and through the row decoder marked as (4). Theselected row voltage level is set to VGND (ground). As the resistivearray cell content is changed from low resistor value (RL) to highresistor value (RH), the current from the resistive array cell (I_load)changes from VREF/RL to VREF/RH. Therefore the current on M1 transistorin (2) changes from “I_fix-VREF/RL” to “I_fix-VREF/RH”. This currentchange detected in the “Current Comparator” in (2) that generates OUT<k>as “Low Voltage Level” if the resistive cell content is “RL” or “HighVoltage Level” if the resistive cell content is “RH”. In other examples,Current Comparator can be designed in such a way that OUT<k> will be at“High Voltage Level” if the resistive cell content is “RL” or “LowVoltage Level” if the resistive cell content is “RH”. Calibrationcircuitry in (2) is considered to adjust the current reference tocompensate process/temperature and voltage variations on each of theelements shown in FIG. 31.

Second Example Read Circuitry—Method II

As the selected resistive ram cell content is changed from RL to RH, theoutput voltage of the opamp in FIG. 32 changes from VREF×(R_fix+RL)/RLto VREF×(R_fix+RH)/RH. Considering R_fix equal to RL and RL=˜RH/10,output voltage of the opamp changes from 2×VREF to ˜1.1VREF. Voltagecomparator converts this variation to “Low Voltage Level” or “HighVoltage Level” depending on the resistive ram cell content. Calibrationcircuitry in (5) is considered to adjust the voltage reference tocompensate process/temperature and voltage variations on each of theelements shown in FIG. 32.

Third Example Write Circuitry

To program “high resistive value—RH” or “low resistive value—RL” on aselected row and selected column, VPGM voltage drop needs to be appliedacross the resistive ram cell. Depending on the polarity of VPGM, thecell content data can be either RL or RH, e.g. applying VPGM to ROW andVGND to column programs the cell content as RH, applying VGND to ROW andVPGM to column programs the cell content as RL, or vice versa. In orderto keep other resistive array cells' value not changed, the voltage dropacross each of the un-selected cells needs to be kept less than “VPGM-

V”. In order to set the voltage levels accordingly, reference voltagegeneration block (10) and digital controller (11) is designed to get theproper VPGM voltage level and proper VLH level by adjusting

V. It is essential to write the entire RSM element with minimum

V in order to limit the current consumption over each row and column.During write operation, all un-selected rows' and columns' voltage levelis set to VLH level.

Fourth Example Writing Protocol

Here after follows a pseudo-code description of the writing protocolthat is described regarding to below assumptions and examples.

RAM Size: N×M (e.g. 128×8)

N: number of rowsM: number of columnsVPGM: Programming voltageVLH: Maximum (or minimum) voltage level that will not change the cellcontentAssumption 1: Applying “VPGM to column” and “VGND to row” changes thecontent of the cell to “RH”. In this case VLH is close to “VPGM”Assumption 2: Applying “VGND to column” and “VPGM to row” changes thecontent of the cell to “RL”. In this case VLH is close to “VGND”

Logic “0”: RL Logic “1”: RH

For instance, N: 128, M: 8, VPGM=1V, VLH=900 mV and RL=10 KΩIf only one cell is written on the selected row:max peak row current for the worst case condition=VPGM/RL=100μAmax peak column current for the worst casecondition=(VPGM−VLH)×(N−1)/RL+VPGM/RL=10 μA×127+100μA=1370 μAIf all cells are written simultaneously on the selected row:max peak row current for the worst case condition=VPGM×M/RL=800 μAmax peak column current for the worst casecondition=(VPGM−VLH)×(N−1)/RL+VPGM/RL=1370 μA

-   1. Assign the data to be written to an 8-bit register (REG1)-   2. READ from the selected row and assign the read-data to another    8-bit register (REG2).    -   i. While Reading, set each un-selected row to “VREF” voltage of        the OpAmp connected to the columns as in (3) and (6) of FIG. 31        and FIG. 32    -   ii. Set selected row to “VGND”-   3. COMPARE the data in REG1 and REG2. If they don't match, start the    WRITE operation. If they matches, select the next row and repeat the    step 2 and step 3.-   4. If REG1 content is not equal to “hex00” then WRITE the content of    the selected row to “hexFF” and go to step 5. If it is equal to    “hex00” then go to step 8 to perform WRITE operation of logic 0s    (RLs).-   5. WRITE Operation of hexFF on the selected row by selecting each    column individually    -   i. Set VLH and VPGM voltage levels to their initial voltage        levels (e.g. 0.9V and 1V)    -   ii. Set all rows and columns to “VLH”.    -   iii. Set selected row to “VGND=0V”    -   iv. Set selected column to be written to “VPGM”    -   v. Worst case peak current calculation (assuming VPGM=1V and        VLH=900 mV)        -   1. Current on the un-selected rows-->Since the maximum            voltage drop across the resistors on the un-selected rows is            “VPGM−VLH=100 mV”, the maximum current could be: 100 mV/RL            (in this example, Imax=100 mV/10 kΩ=10 μA)        -   2. Current on the selected row-->The maximum voltage drop is            “VPGM=1V”. Therefore maximum current is: 1V/RL=100 μA        -   3. Current on the un-selected columns-->Voltage drop across            all resistors except the one on the selected row is “0V”            since both column and row of the un-selected cells are equal            to “VLH”. But the voltage drop of the resistor on the            selected row is “VLH−0V”. Thus, max current on the            un-selected column=VLH/RL (900 mV/10 kΩ=90 μA)        -   4. Current on the selected columns-->-->Voltage drop across            all resistors except the one on the selected row is            “VPGM−VLH=100 mV”. But the voltage drop of the resistor on            the selected row is “VPGM−0V”. Thus, max current on the            selected column=100 mV×(N−1)/RL+VPGM/RL (100 mV×127/10            kΩ+1V/10 kΩ=1270 μA+100 μA=1370 μA-   6. After WRITE operation of hexFF, do READ from the selected row.    Set the column and row voltages according to Step 2.i and Step 2.ii.    And assign the output of this operation to REG2-   7. COMPARE the data in REG2    -   i. Check whether REG2 content is hexFF.    -   ii. If not, it means that VPGM level is not large enough to        program the selected cell. So, increase VPGM and VLH by DV (e.g.        100 mV) and repeat the steps from “5” to “7”    -   iii. If yes, then go to step “8”, WRITE operation of “RLs”.-   8. WRITE operation of all “RL” s on the selected row    -   i. Set the column index to “0” and select the column<0>.    -   ii. Then set all rows and columns to “VLH” and set “VLH” as “100        mV”    -   iii. If REG1<column index>=“0” then perform RL write operation        and go to step 8.iv. If it is not “0” then increase the column        index and go to step 8.ii    -   iv. Set selected row to “VPGM”    -   v. Set the selected column to “VGND”    -   vi. Worst case current calculation (assuming VPGM=1V and VLH=100        mV)        -   1. Current on the un-selected rows-->Since the maximum            voltage drop across the resistors on the un-selected rows is            “VLH−VGND=100 mV”, the maximum current could be: 100 mV/RL            (in this example, Imax=100 mV/10 kΩ=10 μA)        -   2. Current on the selected row-->the maximum voltage drop is            “VPGM=1V”. Therefore maximum current is: 1V/RL=100 μA        -   3. Current on the un-selected columns-->Voltage drop across            all resistors except the one on the selected row is “0V”            since both column and row of the un-selected cells are equal            to “VLH”. But the voltage drop of the resistor on the            selected row is “VPGM−VLH=900 mV”. Therefore, max current on            the un-selected row=VPGM/RL (900 mV/10 kΩ=90 μA)        -   4. Current on the selected columns-->-->Voltage drop across            all resistors except the one on the selected row is            “VLH−VGND=100 mV”. But the voltage drop of the resistor on            the selected row is “VPGM−0V”. Therefore, max current on the            selected row=VLH×(N−1)/RL+VPGM/RL (VLH×127/10 kΩ+1V/10            kΩ=1270 μA+100 μA=1370 μA-   9. After WRITE operation of RLs, do READ from the selected row. Set    the column and row voltages according to Step 2.i and Step 2.ii. And    assign the output of this operation to REG2-   10. COMPARE the data in REG1 and REG2    -   i. Find out whether all RLs of REG1 is programmed correctly.    -   ii. If not, then it means that VPGM is not large enough to        program the selected cell. So, increase VPGM by 100 mV and        repeat the steps from “7” to “8”    -   iii. Find out whether none of the RHs of REG1 is changed to RL        in REG2.    -   iv. If some or all of the RHs changed to “RL”, it means the VLH        need to be set higher than our expectation. So, increase VLH by        50 mV or 100 mV and repeat the steps from “8” to “10”.

In other examples, writing RHs and RLs on the selected row could be donesimultaneously for each column in step 5 and in step 8. If it is thecase then, step 5 and step 8 could be:

5. WRITE Operation of hexFF on the selected row by selecting all columns

-   -   i. Set VLH and VPGM voltage levels to their initial voltage        levels (e.g. 0.9V and 1V)    -   ii. Set all rows and columns to “VLH”.    -   iii. Set selected row to “VGND=0V”    -   iv. Set all columns to “VPGM”    -   v. Worst case peak current calculation (assuming VPGM=1V and        VLH=900 mV)        -   1. Current on the un-selected rows-->Since the maximum            voltage drop across the resistors on the un-selected rows is            “VPGM−VLH=100 mV”, the maximum current could be: 100 mV×M/RL            (in this example, Imax=100 mV×8/10 kΩ=80 μA)        -   2. Current on the selected row-->The maximum voltage drop is            “VPGM=1V”. Therefore maximum current is: 1V×M/RL=800 μA        -   3. Current on the un-selected columns-->Voltage drop across            all resistors except the one on the selected row is “0V”            since both column and row of the un-selected cells are equal            to “VLH”. But the voltage drop of the resistor on the            selected row is “VLH−0V”. Thus, max current on the            un-selected column=VLH/RL (900 mV/10 kΩ=90 μA)        -   4. Current on the selected columns-->-->Voltage drop across            all resistors except the one on the selected row is            “VPGM−VLH=100 mV”. But the voltage drop of the resistor on            the selected row is “VPGM−0V”. Thus, max current on the            selected column=100 mV×(N−1)/RL+VPGM/RL (100 mV×127/10            kΩ+1V/10 kΩ=1270 μA+100 μA=1370 μA

-   8. WRITE operation of all “RL”s on the selected row    -   i. Set all rows and columns to “VLH” and set “VLH” as “100 mV”    -   ii. Select all columns that needs to be written as “RL”    -   iii. Set selected row to “VPGM”    -   iv. Set all selected columns to “VGND”    -   v. Worst case current calculation (assuming VPGM=1V and VLH=100        mV)        -   1. Current on the un-selected rows-->Since the maximum            voltage drop across the resistors on the un-selected rows is            “VLH−VGND=100 mV”, the maximum current could be: 100 mV×M/RL            (in this example, Imax=100 mV×8/10 kΩ=80 μA)        -   2. Current on the selected row-->the maximum voltage drop is            “VPGM=1V”. Therefore maximum current is: 1V×M/RL=800 μA            (assuming only one cell on the selected row is going to be            written)        -   3. Current on the un-selected columns-->Voltage drop across            all resistors except the one on the selected row is “0V”            since both column and row of the un-selected cells are equal            to “VLH”. But the voltage drop of the resistor on the            selected row is “VPGM−VLH=900 mV”. Therefore, max current on            the un-selected row=VPGM/RL (900 mV/10 kΩ=90 μA)        -   4. Current on the selected columns-->-->Voltage drop across            all resistors except the one on the selected row is            “VLH−VGND=100 mV”. But the voltage drop of the resistor on            the selected row is “VPGM−0V”. Therefore, max current on the            selected row=VLH×(N−1)/RL+VPGM/RL (VLH×127/10 kΩ+1V/10            kΩ=1270 μA+100 μA=1370 μA

Description of the RSM Device

As shown in FIG. 35A an RSM is integrated between an electricallyconductive TE and another electrically conductive BE, forming an RSMdevice. The RSM consists of a Resistive Switching Oxide (RSO), which isa transition metal oxide that has the property of modifying itsresistivity upon application of either an electric field or a currentflow at the RSO boundaries, and a Selector (SELL) element (see FIG.35B). The SELL has the property of defining either voltage or currentthresholds to ease the selections of a specific RSM device whenintegrated into arrays of RSM devices and can consist of unipolardiodes, bidirectional diodes, transistor or an additional RSO. The RSOelement consists of a stack, the RSO stack, which is composed of two RSOelements (RSOA and RSOB) connected by an INTErmediate element (INTE).The INTE element can be a transition metal oxide or transition metal ora mix of transition metal oxide layers and transition metal oxides,impacting the functionality of the RSM device.

Fifth Example

The fifth example involves a process exploiting embedded features of theCMOS BEoL and as such, it does not require any lithographic steps. Asshown in FIG. 36A, an MMC layer is connected through a VIA (V1) to theTOP METAL. The MMC layer is embedded in the BEoL by design facing aBOTTOM METAL. The TOP METAL is connected to the lower BOTTOM METALlayers (BMLs) through VIA (V3) and to the Front-End of the Line (FEoL)through VIA (V2). The BOTTOM METAL is connected to the FEoL through VIA(V2). The V2 elements consist of BMLs and other VIA according to theBEoL technology. In the example, the MMC has a certain overlap with anunderneath BOTTOM METAL electrode, and by the rules of the BEoLtechnology, the MMC layer distance with the BOTTOM METAL is in the rangeof nanometers up to tens of nanometers. After a PASSIVATION opening step(FIG. 36B), the MMC layer and a section of the BOTTOM METAL is exposed.Then an RSM or an RSM device is deposited, covering the opening formedby the previous step (see FIG. 36C). In this way an RSM device isformed. The read/write circuit designed in the FEoL is thus connected toRSM elements through the MMC and the BOTTOM METAL, which are connectedto other metal layers of the BEoL as part of the circuit design (donebefore post-processing).

Sixth Example

In the sixth example, the RSM devices are deposited between the lastmetal layer of BEoL and the VIAs underneath. As an illustration, aschematic cross section and a tentative process flow of a co-integratedRSM devices into the CMOS BEoL are shown in FIG. 37. As shown if FIG.37A the BEoL consists of metal lines and passivation layers. Then, inFIG. 37B a passivation via etch step is performed according to apredefined masking step to remove the passivation layer over a metalline. In addition, an UPper MetaL layer (UPML) is etched utilizinganother mask, leaving a residual UPML and VIA (VUB) exposed. The UPML isconnected to BMLs through VUBs. Then an RSM or an RSM device depositionsequence is performed, resulting in the structure shown in FIG. 37C,providing electrical contact between UPMLs and RSM (alternatively, anRSM device) or the UPML and the VUB through the RSM (alternatively, anRSM device), or the VUBs through the RSM (alternatively, an RSM device).The RSMs (alternatively, the RSM devices) are connected to the rest ofthe BEoL through VUBs and UPMLs.

Seventh Example

To reduce the number of masking steps, the present seventh example,using only a unique step, is developed. As shown in FIG. 38A, the CMOSdie is fabricated such that the CMOS BEoL includes patterns that can beused as a mask for the definition of the RSM devices. In this way thepost-processing scheme is dramatically simplified, as it requires onlyone mask for the passivation etch, in case a selective passivationetching is required, or none, in the case where the passivation layersfrom the BMLs are not necessary.

The BEoL post-processing starts from the etching of the passivationlayer FIG. 38B. This can require one masking step to define thepassivation opening area. The passivation opening step is carried out toclear the passivation until at least two metal layers are exposed to theetching process FIG. 38B, for which the UPML is used as a pre-definedetching mask. Then an RSM or an RSM device is deposited on top of theBMLs (see FIG. 38C), to provide an electrically functional connectionbetween different BMLs elements through the RSM elements (or the RSMdevice elements).

Eighth Example

An example of post-processed CMOS chip is shown in the SEM image of FIG.39. The chip BEoL has 6 metal layers and an MMC layer. The MMC layer isconnected with the rest of the BEoL through a VIA and MET6. The MMClayer was designed to overlap with MET5 lines, so to provide anoverlapping region for an RSM or an RSM device to be deposited. In FIG.39, the MET5, MMC and MET6 layers are exposed as a consequence of apassivation etch step.

Perspective Performance

-   -   The read/write operation of resistive memory arrays. In        particular, the invention enables the read/write operation of        large arrays of RSM devices.

The post-processing enables heterogeneous integration of large arrays ofRSM devices with CMOS, beneficial for several applications.

Prospective Applications FPGAs.

In FPGAs, RSM devices can be used as routing resource by employing theresistance of the RSM as a switch. Moreover, two or more RSM devices canbe connected in such a way that a complementary resistive switching cellis formed. This is beneficial for efficient programming of the RSM-basedrouting resources. Similarly, RSM can also be used as standalonememories in FPGAs. The low voltage operation and the high ResistanceRatio enable to scale the technology and to improve noise margins,respectively.

Standalone Memories

A large resistive ratio of the RSM enables to improve noise margin, thusrelaxing the requirements for the peripheral circuitry needed for theread/write operations in standalone memories. It is important to noticethat the scalability and the multi-valued features are extremelyimportant for standalone memories to be competitive.

Dense Cross-Bars

As per the previous application, the scalability and the multi-valuefeatures are keys for dense cross-bar applications.

Neural Networks

Arrays of RSM devices might be implemented in neuromorphic circuits inspecific blocks. For instance, the RSM device can be utilized to emulatethe artificial synapse behavior. Due to the requirements of a largenumber of synaptic interconnections and the capability to store a rangeof resistance states to express potentiation and/or depression of asynaptic interconnect, multi-value and scalability features are alsovery important.

REFERENCES

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1. A bipolar resistive switching device comprising: an electricallyconductive bottom electrode; a stack of transition metal oxides layers,a number of transition metal oxide layers being equal or greater than 2,the stack comprising: at least one MOx layer, at least one oxygengettering layer NO_(y); and the resistive switching device furthercomprises an electrically conductive top electrode.
 2. The switchingdevice of claim 1, wherein the oxygen gettering layer comprises atransition metal oxide taken from the list comprising: CrO_(y), TiO_(y),HfO_(y), NbO_(y).
 3. The switching device of claim 2, wherein a value ofthe stochiometric number y is in the range 0<y≦2.
 4. The switchingdevice of claim 1, wherein values of the stochiometric number x is inthe range 0<x≦2.5.
 5. The switching device of claim 1, wherein the metalM is taken from the list comprising: Cr, Ti, Hf, Ta, Nb.
 6. Theswitching device of claim 1 wherein the stack of transition metal oxidelayer further includes at least one layer of metal (INTE).
 7. A processfor manufacturing a bipolar resistive switching device comprising stepsof creating a bottom electrode from an electrically conductive material,creating a top electrode from an electrically conductive material, andcreating a stack of transition metal oxide layers sandwiched in betweenthe top electrode and the bottom electrode, a number of transition metaloxide layers being equal or greater than 2, the stack comprising atleast one MO_(x) layer, and at least one oxygen gettering layer NO_(y).8. The process of claim 7 wherein the oxygen gettering layer comprises atransition metal oxide NO_(y), wherein the metal N is taken from thelist comprising: Cr, Ti, Hf, Nb.
 9. The process of claim 7, wherein themetal M is taken from the list comprising: Cr, Ti, Hf, Ta, Nb.
 10. Theprocess of claim 7, further comprising a step of creating at least onelayer of metal to be included in the stack of transition metal oxidelayers.
 11. The process of claim 7, whereby the step of creating theelectrically conductive bottom electrode comprises starting from anelectrically insulated Si substrate, and depositing the bottom electrode(BE) lines with a lift-off method, the step of creating the stack ofmetal oxide layers comprises depositing the MO_(x) layer by means ofsputtering from a MO_(z) target, wherein values of the stochiometricnumber z is in the range 0≦z≦2.5, and evaporating a metallic N layerthereby forming the oxygen gettering NO_(y) layer at the interfacebetween N and TaO_(x), and the step of creating the electricallyconductive top electrode comprises starting from the metal oxide layer,and depositing the top electrode lines with a lift-off method.
 12. Theprocess of claim 7 wherein a value of the stochiometric number y is inthe range 0<y≦2.
 13. The process of claim 7, wherein values of thestochiometric number x is in the range 0<x≦2.5.
 14. The process of claim7 for which the electrically conductive electrodes in the steps ofcreating the bottom electrode, and creating the top electrode, and themetal oxide layers in the step of creating the metal oxide layers stack,are obtained by deposition steps which correspond to one of thefollowing: sputtering deposition; evaporation method; atomic layerdeposition.
 15. The process of claim 7, whereby the step of creating thestack of metal oxide layers comprises: depositing the MO_(x) layer bymeans of sputtering from a MO_(z) target, wherein values of thestochiometric number z is in the range 0≦z≦2.5, and evaporating ametallic N layer thereby forming the oxygen gettering NO_(y) layer atthe interface between N and TaO_(x), and the step of creating theelectrically conductive top electrode comprises starting from the metaloxide layer, and depositing the top electrode lines with a lift-offmethod.
 16. The process of claim 15, wherein the step of creating theelectrically conductive bottom electrode comprises depositing bottomelectrode lines starting from a CMOS circuit.
 17. The process of claim15, wherein the step of creating the electrically conductive bottomelectrode comprises starting from a CMOS circuit, the CMOS circuitcomprising conductive electrode lines which are used as the electricallyconductive bottom electrode.
 18. The process of claim 15, wherein thestep of creating the electrically conductive bottom electrode comprisesdepositing bottom electrode lines starting from an electricallyinsulated Si substrate.
 19. The process of claim 15, wherein the step ofcreating the electrically conductive bottom electrode comprises startingfrom an electrically insulated Si substrate, the electrically insulatedSi substrate comprising conductive electrode lines which are used as theelectrically conductive bottom electrode.
 20. A circuit comprising 2bipolar resistive switching devices as described in claim 1, the 2bipolar resistive switching devices being serially connected in such away that their polarities are opposed.
 21. A multiplexer circuitcomprising a plurality of bipolar resistive switching devices andtransistors, wherein the bipolar resistive switching devices serve asrouting switching and wherein transistors serve for programming themultiplexer circuit.
 22. A read/write circuit comprising: a digitalcontroller that has a digital state machine configured to control writeoperation according to a protocol; an analog read circuitry comprising:a high gain differential amplifier, a current comparator and a currentcalibration circuitry designed for a column, whereby the analog readcircuitry comprises a high gain operational amplifier, a voltagecomparator and a voltage calibration circuitry; a further analog readcircuitry to set each un-selected row voltage to the same voltage levelas the column voltage levels; a reference voltage generation blockcontrolled by the digital controller to keep the row and column voltagelevels at sufficient voltage levels in order to program a ResistiveSwitching Material element contents with minimum current consumption;and column and row decoders controlled by the digital controller toselect the appropriate voltage level on the selected row and selectedcolumn.
 23. The read/write circuit of claim 22 wherein a sequence ofwrite operations is applied and verified by a sequence of readoperations to ensure that a specific resistive switching material storesa specific resistance state.
 24. A programming operation of the circuitof claim 20, wherein each one of the voltage signals −5V≦V_(p1)≦+5V,−5V≦V_(p2)≦+5V, −5V≦V_(p3)≦+5V are simultaneously applied to each one ofthe electrodes forming the circuit, causing the two bipolar resistiveswitching devices to simultaneously change resistive state.